In the end synthesis with mapping and place and route of the whole pipeline with all functional blocks takes about one hour on a Pentium-III with 500 MHz. RAM of about 120 MB is needed.
The synthesized circuits consist of 853 Flip-Flops and 109 Latches. It comes to an equivalent gate count of about 27200. All instruction named in table 4.2 but multiplication and division are implemented. This is all priority stages but 2 and 1. The freed space has been used for additional extended Bytecodes to be implemented, so that testing becomes easier and microcodes are not to change.
No problem is the routing of all of the 1296 configurable logic blocks (CLB). Additional pins for testing purposes are connected. Those might undermine a completely adapted best distribution of blocks, so that for an implementation after tests a better timing behaviour and therefore a higher clock frequency can be expected. But even the test implementation reaches an external clock of 20 MHz, which is the maximum frequency of the testboard.
This prototype of a pipeline being capable of direct execution of Java-Bytecode comes to an equivalent gate count of about 27200. That is about 250 % of an Intel 8051 microcontroller (around 11000). This microcontroller is an 8-bit-microcontroller with multiplication and division, internal clock generator and full duplex UART interface that is often used by the industry.
If one liked to compare this design to a 32-bit-processor, an ARM core (Advanced RISC Machine) could be taken. It is also often used by the industry as processor or microcontroller core. Alcatel Microelectronics say that their ARM7TDMI reaches an equivalent gate count of about 40000 with corresponding data and address bus width.