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Write Back Unit

The Write Back Unit (WBU) can be seen in figure 4.13. Data from the execution unit must be stored to stack memory or other registers. It is the same with data from external memory. The delay of one pipeline clock cycle has to be treated in this unit. Therefore the write back unit waits for one cycle before storing memory data.

Figure 4.13: Write Back Unit

This means that only one source of data can be processed per cycle (see figure 4.19). This behaviour might be optimized by combining distribution unit (stack memory unit) and write back unit.

Figure 4.19: Statechart of the Write Back Unit

2000-04-27